|
| IP |
Description |
Features |
| DLL |
Delay locked loop |
Wide Lock Frequency (8MHz~135MHz), 2.3V~3.6V |
| PLL |
Phase locked loop |
Wide Lock Frequency (10MHz~250MHz),
Low jitter Tracking to external SSC input |
| SSCG |
Spread spectrum
clock generator |
On Chip SSCG (+/-2.5%, Center) |
| LVDS Tx |
CMOS/TTL signal
convert to LVDS signal |
Up to 10bit support color depth, 945Mbps/CH, 1.6V~3.6V,
Wide frequency range, Input Jitter Filtering |
| LVDS Rx |
LVDS signal convert to
CMOS/TTL signal |
Up to 12bit support color depth, 945Mbps/CH, 1.6V~3.6V,
Wide Input Vos range, Wide frequency range |
| RSDS |
CMOS/TTL signal convert
to RSDS signal |
Wide frequency range, 1.6V~3.6V, Output skew control |
| Mini-LVDS |
CMOS/TTL signal convert
to mini-LVDS signal |
Wide frequency range, 1.6V~3.6V, Pre-emphasis |
| Oscillator |
Reference clock generator |
2.7V~3.6V, Frequency control |
| DC/DC Converter |
Voltage regulator |
Linear voltage regulator |
| DC Generation |
Reference
voltage generator |
2.2V~3.6V, stable reference voltage level generate
with PVT variation |
| DSP |
Embedded 32bit process for low power and low price. |
Hybrid ISP structure (both support 16bit instruction and 32bit instruction) Operation clock speed : 20~30MHz |
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